Control register

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A control register is a processor register which changes or controls the general behavior of a CPU or other digital device. Common tasks performed by control registers include interrupt control, switching the addressing mode, paging control, and coprocessor control.

Contents

[edit] Control registers in x86 series

[edit] CR0

The CR0 register is 32 bits long on the 386 and higher processors. On x86-64 processors in long mode, it (and the other control registers) are 64 bits long. CR0 has various control flags that modify the basic operation of the processor.

Bit Name Full Name Description
31 PG Paging If 1, enable paging and use the CR3 register, else disable paging
30 CD Cache disable
29 NW Not-write through
18 AM Alignment mask Alignment check enabled if AM set, AC flag set (in EFLAGS register, and privilege level is 3
16 WP Write protect
5 NE Numeric error Enable internal x87 floating point error reporting when set, else enables PC style x87 error detection
4 ET Extension type
3 TS Task switched Allows saving x87 task context only after x87 instruction used after task switch
2 EM  ? If set, no x87 floating point unit present, if clear, x87 FPU present
1 MP Monitor co-processor Controls interaction of WAIT/FWAIT instructions with TS flag in CR0
0 PE Protected Mode Enable If 1, system is in protected mode, else system is in real mode

[edit] CR1

Reserved

[edit] CR2

Contains a value called Page Fault Linear Address (PFLA). When a page fault occurs, the address the program attempted to access is stored in the CR2 register.

[edit] CR3

Typical use of CR3 in address translation with 4 KiB pages.
Typical use of CR3 in address translation with 4 KiB pages.

Used when virtual addressing is enabled, hence when PG bit is set in CR0. CR3 enables the processor to translate virtual addresses into physical addresses by locating the page directory and page tables for the current task. Typically, last 20 bits of CR3 become page directory base register (PDBR).

[edit] CR4

Used in protected mode to control operations such as virtual-8086 support, enabling I/O breakpoints, page size extension and machine check exceptions.

Bit Name Full Name Description
13 VMXE VMX Enable
10 OSXMMEXCPT Operating System Support for Unmasked SIMD Floating-Point Exceptions
9 OSFXSR Operating system support for FXSAVE and FXSTOR instructions Must be set to use SSE instructions
8 PCE Performance-Monitoring Counter enable If set, RDPMC can be executed at any privilege level, else it can only be used in kernel mode (ring 0)
7 PGE Page Global Enabled
6 MCE Machine Check Exception Enables machine check interrupts to occur if set
5 PAE Physical Address Extension Changes page table layout to translate 32-bit virtual address into extended 36-bit physical address
4 PSE Page Size Extensions If unset page size is 4 KiB, else it is increased to 4 MiB, or with PAE, 2 MiB
3 DE Debugging Extensions
2 TSD Time Stamp Disable If set, RDTSC instruction can only be executed when in ring 0, otherwise RDTSC can be used at any privilege level
1 PVI Protected Mode Virtual Interrupts Enables hardware support of virtual interrupt flag (VIF) in protected mode
0 VME Virtual 8086 mode extensions Like the virtual interrupt flag; enabled if set

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